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DOI: 10.5445/IR/1000089975
Veröffentlicht am 25.01.2019

Worst-Case Execution Time Guarantees for Runtime-Reconfigurable Architectures

Damschen, Marvin

Abstract (englisch):
Real-time systems are ubiquitous in our everyday life, e.g., in safety-critical domains such as automotive, avionics or robotics. The correctness of a real-time system does not only depend on the correctness of its calculations, but also on the non-functional requirement of adhering to deadlines. Failing to meet a deadline may lead to severe malfunctions, therefore worst-case execution times (WCET) need to be guaranteed. Despite significant scientific advances, however, timing analysis of WCET guarantees lags years behind current high-performance microarchitectures with out-of-order scheduling pipelines, several hardware threads and multiple (shared) cache layers. To satisfy the increasing performance demands of real-time systems, analyzable performance features are required. In order to escape the scarcity of timing-analyzable performance features, the main contribution of this thesis is the introduction of runtime reconfiguration of hardware accelerators onto a field-programmable gate array (FPGA) as a novel means to achieve performance that is amenable to WCET guarantees. Instead of designing an architecture for a specific applic ... mehr


Zugehörige Institution(en) am KIT Institut für Technische Informatik (ITEC)
Publikationstyp Hochschulschrift
Jahr 2019
Sprache Englisch
Identifikator URN: urn:nbn:de:swb:90-899755
KITopen-ID: 1000089975
Verlag Karlsruhe
Umfang XIII, 106 S.
Abschlussart Dissertation
Fakultät Fakultät für Informatik (INFORMATIK)
Institut Institut für Technische Informatik (ITEC)
Prüfungsdatum 19.12.2018
Referent/Betreuer Prof. J. Henkel
Projektinformation SFB/TRR 89/2 (DFG, DFG KOORD, TRR 89/2 2014)
Externe Relationen Forschungsdaten/Software
Forschungsdaten/Software
Schlagworte Worst-Case Execution Time, WCET, Predictability, FPGA, Runtime Reconfiguration, Reconfigurable Computing, Real-Time Systems, Embedded Systems, Fused CPU-GPU Architectures, Timing Anomaly, Invasive Computing, InvasIC
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