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A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s

Pfau, Johannes; Reuter, Maximilian; Harbaum, Tanja; Hofmann, Klaus; Becker, Jürgen

Abstract:
AES (Advanced Encryption Standard) accelerators are commonly used in high-throughput applications, but they have notable resource requirements. We investigate replacing the AES cipher with ChaCha ciphers and propose the first ChaCha FPGA implementations optimized for data throughput. In consequence, we compare implementations of three different system architectures and analyze which aspects dominate the performance of those.Our experimental results indicate that a bandwidth of 175 Gbit/s can be reached with as little as 2982 slices, whereas comparable state of the art AES accelerators require 10 times as many slices. Taking advantage of the flexibility inherent in the ChaCha cipher, we also demonstrate how our implementation scales to even higher throughputs or lower resource usage (down to 476 slices), benefiting applications which previously could not employ cryptography because of resource limitations.

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Postprint §
DOI: 10.5445/IR/1000123496
Frei zugänglich ab 08.05.2021
Originalveröffentlichung
DOI: 10.1109/SOCC46988.2019.1570548289
Scopus
Zitationen: 1
Dimensions
Zitationen: 1
Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsjahr 2020
Sprache Englisch
Identifikator ISBN: 978-1-72813-483-3
KITopen-ID: 1000123496
Erschienen in 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 3-6 Sept. 2019
Veranstaltung 32nd IEEE International System-on-Chip Conference (SOCC 2019), Singapur, Singapur, 03.09.2019 – 06.09.2019
Verlag Institute of Electrical and Electronics Engineers (IEEE)
Seiten 294–299
Projektinformation DFG, DFG EIN, BE 2134/16-1
Vorab online veröffentlicht am 07.05.2020
Nachgewiesen in Scopus
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