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Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA

Hotfilter, Tim ORCID iD icon 1; Kreß, Fabian ORCID iD icon 1; Kempf, Fabian 1; Becker, Jürgen 1; Baili, Imen
1 Institut für Technik der Informationsverarbeitung (ITIV), Karlsruher Institut für Technologie (KIT)


Computational requirements for deep neural networks (DNNs) have been on a rising trend for years. Moreover, network dataflows and topologies are becoming more sophisticated to address more challenging applications. DNN accelerators cannot adopt quickly to the constantly changing DNNs. In this paper, we describe our approach to make a static accelerator more versatile by adding an embedded FPGA (eFPGA). The eFPGA is tightly coupled to the on-chip network, which allows us to pass data through the eFPGA before and after it is processed by the DNN accelerator. Hence, the proposed solution is able to quickly address changing requirements. To show the benefits of this approach, we propose an eFPGA application that enables dynamic quantization of data. We can fit four number converters on an $1.5mm^2$ eFPGA, which can process 400M data elements per second. We will practically validate our work in the near future, with a SoC tapeout in the ongoing EPI project.

Postprint §
DOI: 10.5445/IR/1000151937
Veröffentlicht am 26.10.2022
Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Technik der Informationsverarbeitung (ITIV)
Publikationstyp Proceedingsbeitrag
Publikationsdatum 18.10.2022
Sprache Englisch
Identifikator ISBN: 978-1-6654-6606-6
KITopen-ID: 1000151937
Erschienen in 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Nicosia, Cyprus, 04-06 July 2022
Veranstaltung IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2022), Nikosia, Zypern, 04.07.2022 – 06.07.2022
Seiten 371-372
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