Improvement of Positive and Negative Feedback Power Hardware-in-the-Loop Interfaces Using Smith Predictor

Power hardware-in-the-loop (PHIL) creates a safe test environment to connect simulations
with real hardware under test (HuT). Therefore, an interface algorithm (IA) must be chosen.
The ideal transformer method (ITM) and the partial circuit duplication (PCD) are popular
IAs, where a distinction is made between voltage- (V-) and current-type (C-) IAs. Depending
on the sample time of the simulator and further delays, simulation accuracy is reduced
and instability can occur due to negative feedback in the V-ITM and C-ITM control loops,
which makes PHIL operation impossible. In the case of positive feedback, such as with
the V-PCD and C-PCD, the delay causes destructive interference, which results in a phase
shift and attenuation of the output signal. In this article, a novel damped Smith predictor
(SP) for positive feedback PHIL IAs is presented, which significantly reduces destructive
interference while allowing stable operation at low linking impedances at V-PCD and high
linking impedances at C-PCD, thus reducing losses in the system. Experimental results
show a reduction in phase shift by 21.17° and attenuation improvement of 24.3% for V-PCD
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at a sample time of 100 μs. The SP transfer functions are also derived and integrated into
the listed negative feedback IAs, resulting in an increase in the gain margin (GM) from
approximately one to three, which significantly enhances system stability. The proposed
methods can improve stability and accuracy, which can be further improved by calculating
the HuT impedance in real-time and dynamically adapting the SP model. Stable PHIL
operation with SP is also possible with SP model errors or sudden HuT impedance changes,
as long as deviations stay within the presented limits.