Towards a scalable data readout system for P̅ANDA

The P̅ANDA experiment at FAIR employs a trigger-less data acquisition (DAQ) concept, requiring a scalable and high-performance readout architecture. In this contribution, a scalable data readout system for the P̅ANDA Micro-Vertex Detector (MVD) is presented. The readout architecture consists of the Torino Amplifier for silicon Strip detector (ToASt) front-end ASIC, the Module Data Concentrator (MDC) ASIC and the custom back-end electronics card based on the Advanced Mezzanine Card (AMC) standard. Based on an established prototype, the MVD readout chain was further developed through incremental integration, including its extension to multiple detector modules to demonstrate scalability. In addition, the system was operated over an extended period at high data throughput, showing stable and error-free operation. Moreover, the status of the design and production of the MDC ASIC and the back-end electronics card are reported in this work. The design progress and prototype results represent a step toward integration of the full readout chain into the P̅ANDA experiment. Furthermore, the back-end electronics card has been conceived as a flexible platform, enabling potential applications beyond this specific application.