Reliable Analog Circuit Design and Computing for Ultra-Resource-Constrained Edge Intelligence

In the rapidly evolving era of Internet of Things (IoT) ecosystem, edge intelligence is moving from conventional embedded SoC platforms to ultra-resource-constrained and low-cost, lightweight application specific systems such as smart packaging, on-skin patches, and batteryless sensors. These applications require extremely low power and low cost, and often demand implementation on flexible or unconventional
substrates. While silicon System-on-Chips (SoCs) deliver high performance, they are frequently unable to satisfy the strict form-factor, cost, and energy constraints of such emerging domains. Large-area electronics and analog computing offer a compelling alternative by enabling bespoke local intelligence directly on non-traditional substrates, thereby reducing the hardware overhead of high-precision digital processing.

However, moving to these emerging large-area substrates introduces significant reliability and security challenges. Unlike standard silicon CMOS, large-area electronics suffer from process variations, environmental drift, and aging, which severely degrade classification accuracy and temporal stability. Also, these analog computing designs are physically exposed at the edge, due to lack of rigid packaging, making them vulnerable to physical attacks such as side-channel analysis. ... mehrEnsuring trustworthiness is uniquely difficult because traditional heavyweight protection mechanisms cannot be applied under such extreme area and power budgets. So, a new class of design methodologies is required that co-optimizes accuracy, power and area.

This dissertation addresses these requirements by developing a cross-layer co-design framework for the reliable and secure design of emerging analog computing paradigms including spiking neuromorphic circuits. It systematically tackles the challenges of variability and fault tolerance through Neural Architecture Search (NAS) and evolutionary methods; introduces power-aware/power-constrained training
to ensure energy efficiency and fault-endurance; and also establishes the comprehensive security and diagnostic methodologies for large-area analog computing circuits. The outcome is a unified methodology that enables robust, energy-efficient, and attack-resilient edge intelligence, even on the most resource constrained and unreliable substrates.