Reliable, Testable and Efficient Mapping of Hyperdimensional Computing for Resource-constrained Edge AI

Edge Artificial Intelligence (AI) systems require machine learning models that operate under strict power and memory constraints, which limits the practicality of conventional deep learning models on many Internet of Things (IoT) devices. Hyperdimensional Computing (HDC) is a brain-inspired learning paradigm that encodes data as high-dimensional binary hypervectors and performs classification using simple associative operations, making it suitable for energy-efficient edge (AI) systems.
However, practical hardware implementations of HDC still face several challenges, including substantial memory requirements for storing hypervector representations, excessive data movement between memory and logic, limited scalability, and susceptibility to faults and noisy inputs.

This thesis addresses key limitations of existing HDC implementations by proposing a scalable and hardware-efficient framework for edge deployment, with a memory-efficient encoding method that eliminates the need to store large hypervector memories.
An on-the-fly hypervector generation mechanism dynamically constructs encoding hypervectors using cyclic digital circuits, removing the requirement for static parameter storage and significantly reducing on-chip memory compared to conventional HDC implementations.
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Additionally, an optimized pipelined Field-Programmable Gate Array (FPGA) architecture is developed to improve computational efficiency.
By combining dynamic hypervector generation, hardware sharing, and pruning techniques, the proposed design reduces resource utilization and increases throughput while maintaining classification accuracy compared to other state-of-the-art HDC accelerators.

To support practical deployment, the proposed architecture is integrated into an open-source end-to-end toolchain that maps Python-based HDC models directly to \ac{FPGA} implementations without requiring high-level synthesis.
The framework supports multiple operating modes, including memoryless encoding, conventional encoding, and pruned HDC models, enabling flexible design exploration, efficient hardware generation, and adaptive edge learning.

Furthermore, to improve system reliability, lightweight fault-tolerance mechanisms are introduced for HDC hardware accelerators.
An absolute-summation-based sensitivity analysis identifies vulnerable regions in Class Hypervector (CHV) memory, enabling selective fault correction with reduced hardware overhead compared to existing approaches.
Additionally, a memory-free fault correction technique eliminates the need to store check bits while maintaining robustness under high fault rates.
Lightweight concurrent error detection mechanisms are also proposed to ensure functional safety by detecting both hardware faults and anomalous inputs, including noisy and out-of-distribution samples, with negligible hardware overhead and no additional latency.

Overall, this thesis advances \ac{HDC} for practical edge-AI deployment by introducing hardware-aware techniques that improve memory efficiency, scalability, reliability, and functional safety. Memory efficiency is enhanced by eliminating the need for large encoder memories, while scalability is improved through pipelining, hardware sharing, and pruning techniques. Runtime reliability is strengthened using edge-oriented error-correction mechanisms, and functional safety is supported through concurrent detection of hardware faults and anomalous inputs. By preserving the lightweight and highly parallel characteristics of HDC while integrating low-overhead reliability mechanisms, this work enables more efficient, scalable, and dependable HDC accelerators for resource-constrained and safety-critical edge applications.