Implications of memory mappings on cache misses

This paper proposes an optimization by an alternative
approach to memory mapping. Low set associativity allows
representing cache lines by corresponding memory areas.
With the help of the notion of temporal reuse in the innermost
loop, the behaviour of values in the cache is modelled.
Combining these values into cache lines so that spatial reuse is
considered demands an alternative memory mapping.
Memory mappings with a low expectation of conflicts
are achieved by the random placement of arrays in memory.
Significant increase of cache misses for a worst case placement is
shown by experiments, as well as cache miss reduction achieved by
improving reuse.