Pipeline synthesis and optimization for reconfigurable custom computing machines

This paper presents a pipeline synthesis and optimization technique
for high-level language programming of reconfigurable Custom
Computing Machines. The circuit synthesis generates hardware
accelerators from a sequential program which exploit the
reconfigurable hardware's parallelism. Program loops are transformed
to structural hardware specifications. The optimization algorithm
uses integer linear programming to balance and pipeline the
circuit's registers. This global optimization determines the minimal
amount of flip-flops necessary for an optimal pipeline throughput.
It also considers the irregular flip-flop distribution on FPGAs.
Standard interface circuitry and a runtime system provide the
connection between the accelerator unit and its host computer. An
integrated compiler invokes the synthesis and produces a program
which downloads, calls and controls its hardware accelerators
automatically.