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Pipeline synthesis and optimization for reconfigurable custom computing machines

Weinhardt, Markus


This paper presents a pipeline synthesis and optimization technique
for high-level language programming of reconfigurable Custom
Computing Machines. The circuit synthesis generates hardware
accelerators from a sequential program which exploit the
reconfigurable hardware's parallelism. Program loops are transformed
to structural hardware specifications. The optimization algorithm
uses integer linear programming to balance and pipeline the
circuit's registers. This global optimization determines the minimal
amount of flip-flops necessary for an optimal pipeline throughput.
It also considers the irregular flip-flop distribution on FPGAs.
Standard interface circuitry and a runtime system provide the
connection between the accelerator unit and its host computer. An
integrated compiler invokes the synthesis and produces a program
which downloads, calls and controls its hardware accelerators

Cover der Publikation
Zugehörige Institution(en) am KIT Institut für Programmstrukturen und Datenorganisation (IPD)
Publikationstyp Buch
Publikationsjahr 1997
Sprache Englisch
Identifikator urn:nbn:de:swb:90-AAA8973
KITopen-ID: 897
Erscheinungsvermerk Karlsruhe 1997. (Interner Bericht. Fakultät für Informatik, Universität Karlsruhe. 1997,1.)
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